Throw Away The Clock
Conventional digital circuits can be thought of as being composed of two major sections. The data transformation uses Boolean Logic to specify how the design manipulates the data, while the control section specifies how the data flows through the design. Traditionally, the control section of the design consists of registers controlled by a central clock signal distributed throughout the design. The overhead and performance issues associated with a clock imposed control mechanism are becoming increasingly burdensome as fabrication advancements allow for faster and larger designs. The clock is the root of many of the difficult issues facing designers today including clock-correlated switching noise, peak currents on power rails, unnecessary power consumption due to clock induced switching, and the difficulty of achieving acceptable performance by integrating designs with multiple clock domains that are not harmonically related.
NULL Convention Logic™ (NCL™) integrates data transformation and control into a single expression, thus yielding inherently clockless, delay insensitive circuits and systems. NCL can enable solutions for digital designs facing these critical power, noise, or system integration issues. No global control — in the form of a clock — is required. Circuits communicate with local handshakes driven by the data rate. For system integration, NCL circuits can be easily mixed-and-matched with clocked circuits, memories and analog components.
The features and benefits of NCL have been demonstrated in over 20 ASICs fabricated in a range of technologies and feature sizes for applications ranging from microcontrollers to smart cards, electronic warfare digital receivers and embedded medical signal processors. All these designs were fully functional on first pass.